In the CMOS device represented by system-on-chip, densification and microfabrication are advanced every year, and the gate length of the MOS transistor is set to 0.1 μm or less, and has reached to tens of nm. On the other hand, thickness reduction of the gate insulating film of a MOS transistor is also advanced, and this thickness reduction technology is becoming indispensable for improvement in short channel characteristics and the rise of driving current of a MOS transistor as a generation progresses.
When making microfabrication of the transistor, the increase of gate leakage current accompanying the thickness reduction of a gate insulating film and the expansion of the depletion layer formed in the silicon substrate side in the gate electrode which includes polysilicon pose a problem. The increase in gate leakage current leads to the increase in the power consumption of the whole chip. With the mobile products represented by the cellular phone, while employment of a high-density CMOS device is required in order to correspond to advanced features, it is necessary to suppress gate leakage current low so that battery duration may not become short too much, either. Therefore, the attempt which uses materials with a high relative dielectric constant (it is hereafter called “high-k material”), such as aluminium oxide (Al2O3) and tantalum oxide (Ta2O5), is performed as a material of a gate insulating film. Expansion of the depletion layer formed in the gate electrode which includes polysilicon causes the thickness enhancement of the gate insulating film on appearance, and lowering of driving ability. Therefore, in order to make reduction of the width of the depletion layer concerned and to realize this, the amount of the impurity introduced into the gate electrode is made to increase, or using a metallic material in which a depletion layer does not generate as a gate electrode material is performed.
Generally, in order to make threshold voltage of a MOS transistor into a moderate value, it is necessary to choose a gate electrode material in which the work function to the silicon substrate has a moderate value. When a metal or a metallic compound is used as a gate electrode material in order to suppress the generation of a depletion layer, in order to set threshold voltage as a moderate value in each of an nMOS transistor and a pMOS transistor, it is usually necessary to change the gate electrode material used with those transistors. This makes the CMOS process complicated.
Then, the technology of preventing the generation of the depletion layer by siliciding the whole gate electrode while setting up appropriately the work function of the gate electrode in both transistors by using polysilicon as a gate electrode material and changing the conductivity type of the impurity which is introduced into the polysilicon concerned with the nMOS transistor and the pMOS transistor is proposed. The gate electrode with which all the regions were silicided is called a FUSI (FUlly SIlicided) gate electrode.
The technology regarding a FUSI gate electrode is disclosed in Nonpatent Literature 1. In Patent References 1-5, the technology regarding the MOS transistor which has a gate electrode including silicide is disclosed.
[Nonpatent Literature 1] B. Tavel et al., “Totally Silicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate(˜2Ω/□) without metal CMP nor etching”, International Electron Device Meeting 2001 (IEDM2001).
[Patent Reference 1] Japanese Unexamined Patent Publication No. 2002-319670
[Patent Reference 2] Japanese Unexamined Patent Publication No. Hei 8-46057
[Patent Reference 3] Japanese Unexamined Patent Publication No. Hei 7-245396
[Patent Reference 4] Japanese Unexamined Patent Publication No. Hei 11-121745
[Patent Reference 5] Japanese Unexamined Patent Publication No. Hei 1-183851